1. Field
This invention relates generally to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a GaN semiconductor device that includes selectively depositing diamond within a thermal via in a backside of a substrate of the device.
2. Discussion
Integrated circuits are typically fabricated by epitaxial fabrication processes that deposit or grow various semiconductor layers on a wafer substrate to provide the circuit components for the device. Substrates for integrated circuits can include various materials, usually semiconductor materials, such as silicon, sapphire, SiC, InP, GaAs, etc. As integrated circuit fabrication techniques advance and become more complex, more circuit components are able to be fabricated on the substrate within the same area and be more closely spaced together. Further, these integrated circuit fabrication techniques allow the operating frequencies of the circuit to increase to very high frequencies, well into the GHz range.
Virtually all electronic components operate in a thermally limited capacity, that is, the performance of the device is limited by the amount of heat that can be dissipated to the environment. The amount of thermal dissipation is proportional to the operating voltages, currents and frequencies of the device, where any increase results in higher power dissipation and thus waste heat. The rise of the electronic device junction temperature in the device is proportional to the thermal resistance between the device channel or junctions and the point at which the heat is released to the environment. Every device has a maximum junction temperature, where operation of the device beyond that temperature results in diminished performance and reliability due to basic limitations of the semiconductor and packaging materials. The desire to operate at higher powers (voltage, current, and/or frequency) drives the need for a reduction in thermal resistance. One example includes microprocessors having clock frequencies that have leveled out and increased processing capability has been enabled by expanding the number of processing cores.
Another example includes gallium nitride (GaN)-based RF and microwave power amplifiers. GaN is a wide bandgap semiconductor and GaN-based high electron mobility transistors (HEMTs) have the ability to operate at both high current and high voltage. This type of operation coupled with fine geometries results in megawatt per square centimeter (MW/cm2) power densities near the gate finger of the device. GaN HEMT devices are typically epitaxial grown on a suitable substrate for these applications, where the substrate needs to be highly thermally conductive, electrically insulative, have a thermal expansion coefficient similar to GaN and provide lattice constant matching for suitable epitaxial growth. Suitable materials that are both highly thermally conductive and electrically insulative are relatively unique. The high power dissipation leads to reduced performance due to ‘self-heating’ effects and also limits the long term reliability due to high junction temperatures.
A high thermally conductive substrate for these devices is necessary so that heat is removed from the device junction through the epitaxial layers and the substrate so that the device is able to operate at high power in a reliable manner. Particularly, as mentioned above, as the temperature of the device increases above some threshold temperature, the electrical performance of the device is reduced, which reduces its high power capability. Further, too high of a temperature within the device reduces its reliability because its time to failure will be reduced. Also, these types of devices are typically high frequency devices, which become smaller in size as the frequency increases, which reduces their ability to withdraw heat. The conductive path for heat generated at the device junction layer in an HEMT device causes the heat to propagate through the epitaxial layers and the substrate and into the device packaging. Therefore, it necessary to provide a high thermally conductive substrate that does not impede the path of the heat exiting the device, and allows the heat to spread out over a larger area. The thickness of the substrate is optimized to provide a low resistance heat path into the packaging from the device and provide the ability to spread the heat out away from the device.
Previously, GaN was grown on sapphire, which has poor thermal conductivity and severely limited the available output power. More recently silicon carbide (SiC) has replaced sapphire as a substrate for GaN. For GaN HEMT devices, silicon carbide (SiC) substrates are currently the industry standard for providing the desirable characteristics of electrically insulating, highly thermally conductive, a close lattice match to that of GaN and a similar thermal expansion coefficient to that of GaN. SiC has a much higher thermal conductivity, but the power dissipation is still limited by thermal constraints and the devices are not allowed to perform at their maximum levels. Although SiC is a good thermal conductor, its thermal conductivity is still limited, and as the junction temperature rises in the device, the ability of the SiC substrate to remove the heat is limited, which limits the output power of GaN HEMT devices, and subsequently their reliability, as discussed above.
It is desirable to provide a suitable substrate for a GaN HEMT device that has a greater thermal conductivity than SiC. Diamond is electrically insulating and has the highest thermal conductivity of any bulk material. However, it is currently not possible to epitaxial grow GaN layers on large area single-crystal diamond substrates for many reasons, including availability, a large lattice constant mismatch and different thermal expansion coefficients.
Efforts have been made in the industry to overcome these problems so as to use diamond substrates in a semiconductor device, such as GaN HEMT devices. For example, it is known in the art to remove the SiC substrate, or other substrate, that the GaN layers can effectively be grown on, and then bond a diamond substrate to the device using a bonding layer. However, there is now a bonding layer of some thickness between the GaN device layers and the diamond substrate that does not have the proper thermal conductivity, and thus affects the ability of heat to be removed from the device through the diamond substrate. Further, because bulk diamond has a low thermal coefficient of expansion, there is still the problem that the difference between the thermal expansion coefficients of the device layers and the substrate causes wafer curvature and possibly epitaxial layer cracking.
Other concepts to improve the thermal conductivity of these types of devices are to replace the substrate altogether with diamond. However, since these diamond substrates are polycrystalline in nature, the GaN must be transferred to diamond substrates or the diamond must be grown on the GaN following removal of the original host substrate. This process is fairly limited due to the large coefficient of thermal expansion (CTE) between GaN and diamond. The CTE mismatch limits the scalability of the process and leads to warped wafers which are not possible to process into transistors.
It is also known in the art to grow diamond on the front-side of the device opposite to the substrate. However, it has been shown that these types of devices have limited improvement in thermal conductivity and heat flow out of the device because heat flow through the substrate is still highly important. Further, GaN layers may not survive the high temperature diamond deposition process, and thus may need to be protected using a thermally resistive layer, which again limits the thermal performance.
Diamond thermal vias have been previously conceived to improve thermal resistance of semiconductor substrates by bringing high thermal conductivity diamond conduits close to the device active area where the heat is most concentrated. A high density of high aspect ratio thermal vias has the advantage of increasing the overall thermal conductivity and power handling of the composite diamond/semiconductor substrate. Large vias with thick diamond filled in the vias is also an attractive approach. Both large and small vias require a selective method to coat and fill the vias to prevent unacceptable wafer bow and potential wafer breakage due to large CTE mismatch.